65c RISC V Instructions - SB Format
19:20
65c RISC V Instructions - SB Format
65b RISC V Instructions U Type
5:44
65b RISC V Instructions U Type
65a Quick review of R, I and S formats
2:22
65a Quick review of R, I and S formats
iNumSys App - Tool to practice Number Systems #binary #hexadecimal #octal #decimals
7:16
iNumSys App - Tool to practice Number Systems #binary #hexadecimal #octal #decimals
3. Number of clock cycles taken when there is no forwarding circuitry
0:37
3. Number of clock cycles taken when there is no forwarding circuitry
2. How many stalls are required in lw data dependency for 6 stage pipeline
0:55
2. How many stalls are required in lw data dependency for 6 stage pipeline
1. Determining number of cycles in 6 stage pipeline
0:31
1. Determining number of cycles in 6 stage pipeline
127. Determining Index | Tag | Byte Offset fields in Cache - Activity
4:27
127. Determining Index | Tag | Byte Offset fields in Cache - Activity
126. Effects of increasing block size on Miss rate
7:18
126. Effects of increasing block size on Miss rate
125. How to find data block in memory and map it to a block in cache.
7:15
125. How to find data block in memory and map it to a block in cache.
124. Example - How to calculate total bits in a Cache
2:32
124. Example - How to calculate total bits in a Cache
123. Address subdivision and actual size of Cache in bits
5:01
123. Address subdivision and actual size of Cache in bits
122. Quick review of Memory Hierarchy and Cache
7:20
122. Quick review of Memory Hierarchy and Cache
116. How to stall a cycle in load data hazards | Hazard Detection Unit
13:31
116. How to stall a cycle in load data hazards | Hazard Detection Unit
121. Tag and Valid bits in Cache with example
5:58
121. Tag and Valid bits in Cache with example
120. Basics of Cache and Direct Cache Mapping
4:48
120. Basics of Cache and Direct Cache Mapping
119. Principal of Locality and Memory Hierarchy Levels
6:22
119. Principal of Locality and Memory Hierarchy Levels
118. Introduction to Memory Hierarchy
3:54
118. Introduction to Memory Hierarchy
117. Pipeline Hazards Detection and Handling - Activity
12:06
117. Pipeline Hazards Detection and Handling - Activity
115. Revised MEM forwarding conditions for Double Data Hazards
7:49
115. Revised MEM forwarding conditions for Double Data Hazards
114. Double Data Hazards
10:54
114. Double Data Hazards
113. Forwarding Signals | Activity
7:13
113. Forwarding Signals | Activity
112. Forwarding Path | Activity
2:13
112. Forwarding Path | Activity
111. Updated forwarding conditions for instructions to not write to registers | forwarding hardware.
12:45
111. Updated forwarding conditions for instructions to not write to registers | forwarding hardware.
110. Conditions to decide when and from which pipelines register to forward the data from.
13:05
110. Conditions to decide when and from which pipelines register to forward the data from.
109. Pipeline Control
6:57
109. Pipeline Control
108. How pipeline registers help writing the correct register value to memory in SW instructions.
3:16
108. How pipeline registers help writing the correct register value to memory in SW instructions.
107. Correct path to define destination register Rd
5:50
107. Correct path to define destination register Rd
106. What are Pipeline Registers and why do we need them?
4:22
106. What are Pipeline Registers and why do we need them?
105. Which path causes the data and control hazards in pipeline architecture?
3:13
105. Which path causes the data and control hazards in pipeline architecture?