M.Tech in IC Technology.Worked in DRDO,Hyderabad as a Project Engineer (VLSI/ELECTRONICS R&D)

#5 Verilog Interview Questions and Answers || verilog Q & A series
30:02
#5 Verilog Interview Questions and Answers || verilog Q & A series
#4 Verilog Interview Questions and Answers || verilog Q & A series
33:44
#4 Verilog Interview Questions and Answers || verilog Q & A series
#3 Verilog Interview Questions and Answers || verilog Q & A series
10:34
#3 Verilog Interview Questions and Answers || verilog Q & A series
#2 Verilog Interview Questions and Answers || Verilog Interview Q &A series
10:47
#2 Verilog Interview Questions and Answers || Verilog Interview Q &A series
#1 Verilog Interview Questions and Answers || verilog Interview Q&A series
16:03
#1 Verilog Interview Questions and Answers || verilog Interview Q&A series
RTL based Memory Verification || How industry standard Testbench is written for Verification
31:37
RTL based Memory Verification || How industry standard Testbench is written for Verification
RTL based Verification || functional verification ||Types of testbench ||Stimulus,driver,DUT,monitor
32:29
RTL based Verification || functional verification ||Types of testbench ||Stimulus,driver,DUT,monitor
VLSI Design Flow || specification to GDS2 ||Both FPGA and ASIC design flow || what exactly is GDSII
33:06
VLSI Design Flow || specification to GDS2 ||Both FPGA and ASIC design flow || what exactly is GDSII
#38-1 Difference between REG and WIRE in verilog, their physical meaning,How to choose REG and WIRE
16:40
#38-1 Difference between REG and WIRE in verilog, their physical meaning,How to choose REG and WIRE
FPGA based project || RUBIC cube solver || Project link provided
3:13
FPGA based project || RUBIC cube solver || Project link provided
Square wave extension digital logic diagram with explanation || interview question
6:44
Square wave extension digital logic diagram with explanation || interview question
#19-1 Blocking and Non Blocking assignment in a always Block || very important concept
20:59
#19-1 Blocking and Non Blocking assignment in a always Block || very important concept
#41 Hardware implementation of FSM ||understand FSM diagram and how to draw digital circuit from FSM
39:12
#41 Hardware implementation of FSM ||understand FSM diagram and how to draw digital circuit from FSM
#18-1 How multiple #0 delays are executed in verilog || zero delay control in verilog
6:52
#18-1 How multiple #0 delays are executed in verilog || zero delay control in verilog
#3-1 Number representation in verilog || Number format in verilog
7:32
#3-1 Number representation in verilog || Number format in verilog
#2-1 Replicate & Concatenation operator in verilog|| Most used operator in verilog ||very important
5:27
#2-1 Replicate & Concatenation operator in verilog|| Most used operator in verilog ||very important
SET UP & HOLD TIME ||it's physical meaning|| it's importance||How it's related to CMOS, Capacitor
52:24
SET UP & HOLD TIME ||it's physical meaning|| it's importance||How it's related to CMOS, Capacitor
Edge Detection Logic||Explanation with digital filter & verilog code || Different clock in same code
15:39
Edge Detection Logic||Explanation with digital filter & verilog code || Different clock in same code
#4-1 STRING Data type in verilog || Data type in verilog
4:06
#4-1 STRING Data type in verilog || Data type in verilog
#12-1 Use of always@(*) in verilog || combinatioal logic design in verilog || very important concept
9:47
#12-1 Use of always@(*) in verilog || combinatioal logic design in verilog || very important concept
#10-1 Difference between GATE level and STRUCTURAL Modelling in verilog || interview question
7:26
#10-1 Difference between GATE level and STRUCTURAL Modelling in verilog || interview question
#31-1 forever vs always vs initial in verilog ||forever in verilog||always, initial ||very important
11:32
#31-1 forever vs always vs initial in verilog ||forever in verilog||always, initial ||very important
Difference between VERIFICATION, TESTING & VALIDATION in VLSI Design
30:14
Difference between VERIFICATION, TESTING & VALIDATION in VLSI Design
VLSI Project || DAC( Digital to Analog Converter) interfacing with FPGA using SPI || SPARTAN 3E
43:31
VLSI Project || DAC( Digital to Analog Converter) interfacing with FPGA using SPI || SPARTAN 3E
LCD Interfacing with FPGA ||Working verilog code||Working principle is same for Microcontroller also
42:22
LCD Interfacing with FPGA ||Working verilog code||Working principle is same for Microcontroller also
(Part -3) Digital logic SYNTHESIS || why synthesis || Synthesis flow || Synthesis interview question
49:01
(Part -3) Digital logic SYNTHESIS || why synthesis || Synthesis flow || Synthesis interview question
( Part -2 ) RTL Coding Guidelines || What is RTL || RTL Code = verilog code + RTL coding guidelines
1:08:12
( Part -2 ) RTL Coding Guidelines || What is RTL || RTL Code = verilog code + RTL coding guidelines
VLSI Project || RF based WIRELESS data transmission between two FPGA ||SPI || NRF24L01||Verilog Code
1:08:20
VLSI Project || RF based WIRELESS data transmission between two FPGA ||SPI || NRF24L01||Verilog Code
( Part -1 ) SPEC in VLSI Design|| Datasheet for chip designing || Frontend Design flow
25:23
( Part -1 ) SPEC in VLSI Design|| Datasheet for chip designing || Frontend Design flow
I2C protocol with Verilog code || Onboard I2C controlled EEPROM Interfacing with FPGA
1:35:43
I2C protocol with Verilog code || Onboard I2C controlled EEPROM Interfacing with FPGA