What the Bug - VideoAndMovie

I post videos about ASIC design and Verification

GenAI Writes Verilog, Simulates, and Summarizes!

9:45

GenAI Writes Verilog, Simulates, and Summarizes!

RTL2UVM:Automated UVM Testbench Generation for Verilator with LLM Assistant

35:52

RTL2UVM:Automated UVM Testbench Generation for Verilator with LLM Assistant

RTL to UVM: See Your Testbench Come to Life with UVM testbench generator

7:24

RTL to UVM: See Your Testbench Come to Life with UVM testbench generator

UVM Reactive Stimulus: FIFO Verification

1:30:33

UVM Reactive Stimulus: FIFO Verification

UVM Testbench Generator: APB DEMO

46:19

UVM Testbench Generator: APB DEMO