series parallel Network Analysis and Synthesis remedial class
4:29
series parallel Network Analysis and Synthesis remedial class
Phasor diag RL RC Network analysis and synthesis remedial
21:37
Phasor diag RL RC Network analysis and synthesis remedial
duality theorem Network Analysis and Synthesis remedial class
6:23
duality theorem Network Analysis and Synthesis remedial class
s domain transform Network Analysis and Synthesis remedial class
3:21
s domain transform Network Analysis and Synthesis remedial class
power triangle Network analysis and synthesis remedial class
3:34
power triangle Network analysis and synthesis remedial class
Two port networks- Network Analysis and Synthesis Remedial class
17:35
Two port networks- Network Analysis and Synthesis Remedial class
constant K LPF HPF- Network Analysis and Synthesis- Remedial class
16:14
constant K LPF HPF- Network Analysis and Synthesis- Remedial class
Foster form I and II- Network Analysis and Synthesis- Remedial class
11:42
Foster form I and II- Network Analysis and Synthesis- Remedial class
Cauer form I and II- Network Analysis and Synthesis- Remedial class
9:02
Cauer form I and II- Network Analysis and Synthesis- Remedial class
Control systems- Nyquist plot basics and problem
34:04
Control systems- Nyquist plot basics and problem
Network analysis and synthesis- DC transients remedial class
24:36
Network analysis and synthesis- DC transients remedial class
Network analysis and synthesis- Resonance remedial class
22:44
Network analysis and synthesis- Resonance remedial class
Control systems- state variable analysis overview
13:12
Control systems- state variable analysis overview
Control systems- freq domain spec bodeplot compensators overview
14:22
Control systems- freq domain spec bodeplot compensators overview
Control systems- Root locus overview
14:45
Control systems- Root locus overview
Control systems- RH Criteria overview
12:53
Control systems- RH Criteria overview
Control systems- Polar plot problem on graph sheet
29:11
Control systems- Polar plot problem on graph sheet
2x1 MUX using transmission gates in cadence
21:05
2x1 MUX using transmission gates in cadence
CMOS NOR Gate in cadence
13:06
CMOS NOR Gate in cadence
CMOS NAND gate in cadence
13:55
CMOS NAND gate in cadence
RH Criteria L6
8:46
RH Criteria L6
theory problem- combining pipelining and parallel processing for power reduction in FIR 3 tap filter
5:32
theory problem- combining pipelining and parallel processing for power reduction in FIR 3 tap filter
problem parallel processing and power reduction in FIR 3 tap filter
14:48
problem parallel processing and power reduction in FIR 3 tap filter
parallel processing and power reduction in FIR 3 tap filter
8:15
parallel processing and power reduction in FIR 3 tap filter
problem pipelining and power reduction in FIR 3 tap filter
15:22
problem pipelining and power reduction in FIR 3 tap filter
pipelining and power reduction in FIR 3 tap filter
12:48
pipelining and power reduction in FIR 3 tap filter
simulink 2nd order differential equ
8:40
simulink 2nd order differential equ
simulink step res 1st order 2nd order 4 types
11:36
simulink step res 1st order 2nd order 4 types
control sys- matalb- TF imp step ram resp 2nd order step responses undamped under
11:50
control sys- matalb- TF imp step ram resp 2nd order step responses undamped under
Testing and package classification VLSI Tech
12:58
Testing and package classification VLSI Tech