一般社団法人RISC-V協会は、オープンなRISC-V、および、RISC-Vをエネーブルするオープンな半導体技術、RISC-Vがエネーブルするオープンなシステム技術を日本国内および周辺諸国に広める活動をしています。

RISC-V Alliance Japan was incorporated as a non-profit organization in Japan. The purpose is to proliferate RISC-V, open silicon technology enabling RISC-V, and system technology enabled by RISC-V to Japan and neighboring countries. Strongly motivated to ally with RISC-V organizations worldwide.

Poster session review and award winners announcement
3:32
Poster session review and award winners announcement
The Future of RISC-V Development Paved by Kubuds: Cross Toolchain and Optimization Technology
39:09
The Future of RISC-V Development Paved by Kubuds: Cross Toolchain and Optimization Technology
Transforming Modern Computing With RISC-V Charlie Hong-Men Su | CTO & President, Andes Technology
44:51
Transforming Modern Computing With RISC-V Charlie Hong-Men Su | CTO & President, Andes Technology
テンストレント最先端デジタルSoC設計人材育成/上級コースのご紹介：中野 守 | 代表取締役社長　テンストレントジャパン株式会社（米国）
12:01
テンストレント最先端デジタルSoC設計人材育成/上級コースのご紹介：中野 守 | 代表取締役社長　テンストレントジャパン株式会社（米国）
Value of RISC-V That Empowers ISO26262 Certified Chip | Frankwell Jyh-Ming Lin | Andes Technology
13:19
Value of RISC-V That Empowers ISO26262 Certified Chip | Frankwell Jyh-Ming Lin | Andes Technology
RISC-V Day Tokyo 2025 Autumnの案内：RISC-V DAY TOKYO 2025 SPRING 2025年2月27日　河崎俊平 | RiSC-V協会　理事長（日本）
2:44
RISC-V Day Tokyo 2025 Autumnの案内：RISC-V DAY TOKYO 2025 SPRING 2025年2月27日　河崎俊平 | RiSC-V協会　理事長（日本）
我が国の半導体・デジタル産業戦略について： 齋藤 尚史 | 経済産業省 商務情報政策局 情報産業課・課長補佐
25:29
我が国の半導体・デジタル産業戦略について： 齋藤 尚史 | 経済産業省 商務情報政策局 情報産業課・課長補佐
東京大学d.labとTenstorrentの連携による次世代半導体技術者育成プログラム
9:11
東京大学d.labとTenstorrentの連携による次世代半導体技術者育成プログラム
RISC-V CPUコア、22nm超低リーク・プロセス、およびReRAM不揮発メモリ技術を使用したパワエレ制御向けMCU MD6605の開発 山崎尊永 | サンケン電気
25:09
RISC-V CPUコア、22nm超低リーク・プロセス、およびReRAM不揮発メモリ技術を使用したパワエレ制御向けMCU MD6605の開発 山崎尊永 | サンケン電気
ARC-V プロセッサ IP の紹介、RISC-V ISA の最適化された実装　田辺　聡、IP グループ スタッフ アプリケーション エンジニア | シノプシス（米国）
30:48
ARC-V プロセッサ IP の紹介、RISC-V ISA の最適化された実装　田辺　聡、IP グループ スタッフ アプリケーション エンジニア | シノプシス（米国）
February 27, 2025 12:45-13:00: Introduction of Poster Session Presenters | Hironori Nakajo (Japan)
12:50
February 27, 2025 12:45-13:00: Introduction of Poster Session Presenters | Hironori Nakajo (Japan)
Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications by Siwinski | Arteris
26:30
Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications by Siwinski | Arteris
MIPSのマルチスレッド対応、安全性で高効率なRISC-Vコンピュートソリューションが駆動する 自律システム向けプラットフォーム
23:36
MIPSのマルチスレッド対応、安全性で高効率なRISC-Vコンピュートソリューションが駆動する 自律システム向けプラットフォーム
SiFive's Leadership in RISC-V in the AI ​​Compute Era by Yoshito Kondo | CEO, SiFive Japan (USA)
35:44
SiFive's Leadership in RISC-V in the AI ​​Compute Era by Yoshito Kondo | CEO, SiFive Japan (USA)
Beyond Innovation: RISC-V’s Path to Mass Adoption with Mature IP by Wei-Han Lien | Tenstorrent (USA)
34:03
Beyond Innovation: RISC-V’s Path to Mass Adoption with Mature IP by Wei-Han Lien | Tenstorrent (USA)
Hideharu Amano Feb 27 2025 RISC-V Day Tokyo 2025 Spring Welcome Remark
5:52
Hideharu Amano Feb 27 2025 RISC-V Day Tokyo 2025 Spring Welcome Remark
Detailed Protocol for Integrating 2nm Product Designs into Rapidus Corporation's Foundry Services
58:16
Detailed Protocol for Integrating 2nm Product Designs into Rapidus Corporation's Foundry Services
Evaluation and Award Announcement for the Poster Session at RISC-V Day Tokyo 2024 Summer
3:09
Evaluation and Award Announcement for the Poster Session at RISC-V Day Tokyo 2024 Summer
Advanced Semiconductor Education: Fostering Future Engineers with VLSI Design and Education Center
14:38
Advanced Semiconductor Education: Fostering Future Engineers with VLSI Design and Education Center
RISC-V Adoption Powered by AI, Travis Lanier | VP of Marketing & Product at Ventana Micro Systems
14:43
RISC-V Adoption Powered by AI, Travis Lanier | VP of Marketing & Product at Ventana Micro Systems
All-in-one RISC-V AI Compute Engine for Software Defined Everything, Volker Politz, Semidynamics
19:21
All-in-one RISC-V AI Compute Engine for Software Defined Everything, Volker Politz, Semidynamics
General-Purpose RISC-V Flash MCU “R9A02G021”, 64-bit MPU “RZ/Five”, and RISC-V 32-bit ASSP
30:07
General-Purpose RISC-V Flash MCU “R9A02G021”, 64-bit MPU “RZ/Five”, and RISC-V 32-bit ASSP
Building a RISC-V Ecosystem to Promote Innovation in Heterogeneous Computing by Verisilicon
18:31
Building a RISC-V Ecosystem to Promote Innovation in Heterogeneous Computing by Verisilicon
Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips by Mori Yuji | Lauterbach Japan
22:52
Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips by Mori Yuji | Lauterbach Japan
Expectations for SoCs and Processors in Automotive Systems - For the Advancement of Embedded Systems
15:54
Expectations for SoCs and Processors in Automotive Systems - For the Advancement of Embedded Systems
10-minute position statement in the Japanese region by Frankwell Jyh-Ming Lin | Andes Technology
19:10
10-minute position statement in the Japanese region by Frankwell Jyh-Ming Lin | Andes Technology
Overview and Activities of Leading-edge Semiconductor Technology Center (LSTC): Masahiko Mori | LSTC
14:45
Overview and Activities of Leading-edge Semiconductor Technology Center (LSTC): Masahiko Mori | LSTC
Tenstorrent’s Collaborations with the Japanese Industry by Yasuo Ishii, August 1, 2024, RISC-V Day
15:44
Tenstorrent’s Collaborations with the Japanese Industry by Yasuo Ishii, August 1, 2024, RISC-V Day
{Special Feature: Japan's Semiconductor Strategy 2024 1/2} Introduction, Shumpei Kawasaki
0:50
{Special Feature: Japan's Semiconductor Strategy 2024 1/2} Introduction, Shumpei Kawasaki
Introduction of Poster Session Presenters by Hironori Nakajo | Professor, TUAT (Japan) Aug 1, 2024
17:15
Introduction of Poster Session Presenters by Hironori Nakajo | Professor, TUAT (Japan) Aug 1, 2024